RISC-V & FreeRTOS
- 1 Prerequisites
- 2 RISC-V Cores
- 3 Programming The Demo
- Linux Operating System (this guide uses Ubuntu 20.04)
- Developer Tools (git, make, gcc, python (3))
- Quartus Prime (this guide uses version 20.1 Lite)
- USB Blaster or OpenOCD
- SpiderSoM-S, MX10-S8 or MX10-U
- optionally LED Pmod
Instructions starting with $ are commands to be executed in the terminal.
The working directory is to be taken from context.
Three open source RISC-V cores have been made available for the Intel Platform Designer (Qsys).
To install the cores for Intel Platform Designer, first download the source from the GitHub repository.
- $ git clone https://github.com/ARIES-Embedded/riscv-on-max10.git
Then copy the cores to a location such as /opt/riscv-cores
- $ cp --parents riscv-on-max10/RiscvCores /opt/riscv-cores
Start Intel Quartus Prime and add the cores to the global library:
- Open the menu Assignments -> Settings
- Under IP Settings -> IP Catalog Search Locations add the path
- /opt/riscv-cores/**/* to the global IP search directories
Now the cores are available as IP under the group RISC-V.
Programming The Demo
A precompiled memory initialization file (.mif) is available in the Prebuild/ folder, that can be used to skip this section.
Installing The GNU GCC Toolchain
The complete guide for installing the toolchain can be found in the RISC-V GNU Toolchain repository.
Download and install the prerequisites:
- $ sudo apt-get install autoconf automake autotools-dev curl python3 libmpc-dev libmpfr-dev libgmp-dev gawk build-essential bison flex texinfo gperf libtool patchutils bc zlib1g-dev libexpat-dev
Clone the repository:
Configure build with multilib support for RV32 architectures:
- $ cd riscv-gnu-toolchain
- $ ./configure --prefix=/opt/riscv --with-multilib-generator="rv32i-ilp32--;rv32im-ilp32-rv32ima-;rv32imc-ilp32-rv32imac-;rv32imafc-ilp32f--"
Finally start the build, note that this can take some time!
- $ sudo make
Add the build tools to the path variable by opening ~/.bashrc or equivalent and add the line:
- export PATH="$PATH:/opt/riscv/bin"
Reload the terminal:
- $ source ~/.bashrc
Now the build tools are available via:
Compiling The RISC-V Firmware
Open a terminal in the RiscvSimple/ or RiscvFreertos/ folder of one of the sample projects and run the command:
- $ make
If successful the output files are generated in the subfolder out/.
Copy the bootrom.mif to the respective Quartus Project folder.
- $ cp out/bootrom.mif ..
Quartus Prime Project
Precompiled programming files are available for the modules, they can be used to skip the next section and start with programming the FPGA.
Compiling The Quartus Project
Start Quartus Prime and open the project corresponding to your module.
Click on Start Compilation If successful, the programming files are generated in the folder output_files
Programming the FPGA
The FPGA stores its configuration in the internal SRAM. The configuration is lost when the device is powered down. At bootup the FPGA loads the configuration image from the internal FLASH to the SRAM. The .sof file will only write to the SRAM, usually used for testing and debugging, whereas the .pof file writes to the FLASH and reboots the FPGA. This image will then be loaded whenever the FPGA is powered on. The .pof file is usually used for deploying.
Programming Via USB-Blaster
Start Quartus Prime and open the Programmer. If no programming file is specified, click Add File and navigate to the Prebuild/ or output_files folder and select the appropriate file for the module. Then under Hardware Setup... select the USB-Blaster. Finally press Start.
Programming Via OpenOCD
If not done already install and configure OpenOCD. Then open a terminal and use the command with the .svf file:
- $ mx10spider_prog <path/to/file.svf>
Example: To program the SpiderSoM with the prebuild ".sof" file.
- $ mx10spider_prog Prebuild/Spider_S.svf