Difference between revisions of "RISC-V & FreeRTOS"
From spiderboard.org
								
												
				 (Created page with "== Installing VectorBlox ORCA Core and RISC-V Tools ==  * Download the source from [https://github.com/VectorBlox/orca https://github.com/VectorBlox/orca] using git. *: In thi...")  | 
				|||
| Line 15: | Line 15: | ||
== Compiling Firmware ==  | == Compiling Firmware ==  | ||
| − | * Download [ftp://ftp.aries-embedded.de/products/MX10/software/demo/20190506_SpiderSoM_quartus_riscv_freertos.zip RISC-V Example] and unpack.  | + | * Download the [ftp://ftp.aries-embedded.de/products/MX10/software/demo/20190506_SpiderSoM_quartus_riscv_freertos.zip RISC-V & FreeRTOS Example] and unpack.  | 
* Open a terminal window, change directory to either ''riscv_freertos_example/riscv'' or ''riscv_freertos_example/riscv_freertos'' and run:  | * Open a terminal window, change directory to either ''riscv_freertos_example/riscv'' or ''riscv_freertos_example/riscv_freertos'' and run:  | ||
*: '''$''' make  | *: '''$''' make  | ||
| Line 44: | Line 44: | ||
* [https://github.com/VectorBlox/orca VectorBlox ORCA]  | * [https://github.com/VectorBlox/orca VectorBlox ORCA]  | ||
| − | * [ftp://ftp.aries-embedded.de/products/MX10/software/demo/20190506_SpiderSoM_quartus_riscv_freertos.zip RISC-V Example]  | + | * [ftp://ftp.aries-embedded.de/products/MX10/software/demo/20190506_SpiderSoM_quartus_riscv_freertos.zip RISC-V & FreeRTOS Example]  | 
Revision as of 14:09, 6 May 2019
Contents
Installing VectorBlox ORCA Core and RISC-V Tools
-  Download the source from https://github.com/VectorBlox/orca using git.
- In this guide the install locations /opt/orca/ and /opt/riscv/ were chosen.
 
 -  Open a terminal window and run:
- $ git clone https://github.com/VectorBlox/orca.git /opt/orca
 - $ cd /opt/orca/tools/riscv-toolchain/
 - $ export RISCV_INSTALL="/opt/riscv"
 -  $ ./build-toolchain.sh
- Info: This may take a while.
 
 
 -  Finally add the RISC-V tools to your path:
- $ nano ~/.profile
 
 
- export PATH=/opt/riscv/bin:$PATH
 
Compiling Firmware
- Download the RISC-V & FreeRTOS Example and unpack.
 -  Open a terminal window, change directory to either riscv_freertos_example/riscv or riscv_freertos_example/riscv_freertos and run:
- $ make
 
 - The folder out now contains the bootrom.mif (Memory Initalization File).
 - Copy the bootrom.mif to riscv_freertos_example/quartus
 
Quartus Prime Project
-  Open Quartus Prime and load the project under riscv_freertos_example/quartus.
- INFO: This Quartus project is specific to the SpiderSoM - for the MX10 the pin assignment has to be changed.
 
 -  Open Assignments -> Settings -> IP Settings -> IP Catalog Search Locations and add the search path to ORCA.
- If ORCA was installed under /opt/orca/ then use as search path: /opt/orca/**/*
 
 -  (Optional) Open the Platform Designer with the Qsys file
- (Optional) Under System Contents, select onchip_memory2_0 and under memory initialization provide your bootrom.mif file. (The default is to use the bootrom.mif in the quartus folder)
 - (Optional) Save and Generate the Qsys system.
 
 - Compile the project and program it onto the FPGA using either OpenOCD or USB-Blaster.
 
After programming:
- If the red LED on the module starts blinking once per second, the FPGA was programmed successfully.
 - If the green LED on the module starts blinking once every two seconds, the RISC-V Core and its firmware is working.
 - PMod J2 will output a binary counter.
 -  You can use the UART of the FPGA by using standard tools such as picocom:
- $ sudo picocom -b 115200 /dev/ttyACM0
 
- Every character written is looped back and should be displayed on the terminal.