Difference between revisions of "Spiderboard SoM"

From spiderboard.org
Jump to: navigation, search
Line 31: Line 31:
The following components are available for download:
The following components are available for download:
* [ftp://ftp.aries-embedded.de/products/Spiderboard/SpiderSoM/spidersom_V1.1_project_2018-04-06.tar.gz KiCad Project Files]
* [ftp://ftp.aries-embedded.de/products/Spiderboard/SpiderSoM/spidersom_V1.2_schematics_2018-05-16.pdf PDF-Schematics]
* [ftp://ftp.aries-embedded.de/products/Spiderboard/SpiderSoM/spidersom_V1.1_bom_2018-04-06.csv Bill of Materials]
* [ftp://ftp.aries-embedded.de/products/Spiderboard/SpiderSoM/spidersom_V1.2_project_2018-05-16.zip KiCad Project Files]
* [ftp://ftp.aries-embedded.de/products/Spiderboard/SpiderSoM/spidersom_V1.1_gerber_2018-04-06.tar.gz Gerber Data]
* [ftp://ftp.aries-embedded.de/products/Spiderboard/SpiderSoM/spidersom_V1.2_bom_2018-05-26.csv Bill of Materials]
* [ftp://ftp.aries-embedded.de/products/Spiderboard/SpiderSoM/spidersom_V1.2_gerber_2018-05-16.zip Gerber Data]

Revision as of 10:46, 26 September 2018

About SpiderSoM

The SpiderSoM is a programmable, non-volatile solution based on Intel® MAX®10 FPGA, which enables it to deliver full-featured FPGA capabilities: support for various soft-core CPUs, video-processing algorithms, etc. The SpiderSoM promotes the free and open design concept: all resources, like i.e. design files, gerber, source code, etc. are available under certain open licenses. The SpiderSoM is available as a low cost and extremely flexible platform which enables user to setup a running system according to the required specification in a very short time.


This module can be considered as a cost-optimized alternative to the MX10 module.


  • MAX 10 FPGA in F256 package
  • module supports wide range of the devices: from 10M04DC to 10M50DA
  • optional 4 MByte SPI NOR
  • optional 4 GByte e.MMC
  • optional 128/256/512MByte DDR3 DRAM (for 10M 16/25/40/50 FPGAs)
  • programmable clock generator and PLL, with optional external reference input
  • 178 FPGA GPIO pins, including 13 LVDS transmitters and 54 receivers
  • RTC with battery backup
  • programmable high-efficient PMIC, FPGA IO voltages are configurable
  • optional Li-Ion/Li-Pol charger
  • Size: 70mm x 35mm

Block Diagram



The SpiderSoM is an Open Hardware. All design files are available under CERN_OHL_V1.2


The following components are available for download: