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Installing VectorBlox ORCA Core and RISC-V Tools

  • Download the source from https://github.com/VectorBlox/orca using git.
    In this guide the install locations /opt/orca/ and /opt/riscv/ were chosen.
  • Open a terminal window and run:
    $ git clone https://github.com/VectorBlox/orca.git /opt/orca
    $ cd /opt/orca/tools/riscv-toolchain/
    $ export RISCV_INSTALL="/opt/riscv"
    $ ./build-toolchain.sh
    Info: This may take a while.
  • Finally, add the RISC-V tools to your path. Open .profile in your home directory with a text exitor and add the line:
    export PATH=/opt/riscv/bin:$PATH
  • After updating the path variable you may need to logout and login again or run the following command in the terminal:
    $ source ~/.profile

Compiling Firmware

Terminal after calling make.
  • Download the RISC-V & FreeRTOS Example and unpack.
  • Open a terminal window, change directory to either riscv_freertos_example/riscv (for the RISC-V demo) or riscv_freertos_example/riscv_freertos (for the RISC-V FreeRTOS demo) and run:
    $ make
  • The folder out now contains the bootrom.mif (Memory Initalization File).
  • Copy the bootrom.mif to riscv_freertos_example/quartus

Quartus Prime Project

Type in the search path and then click on Add.
  • Open Quartus Prime and load the project under riscv_freertos_example/quartus.
    INFO: This Quartus project is specific to the SpiderSoM - for the MX10 the pin assignment has to be changed.
  • Open Assignments -> Settings -> IP Settings -> IP Catalog Search Locations and add the search path to ORCA.
    If ORCA was installed under /opt/orca/ then use as search path: /opt/orca/**/*
  • (Optional) Launch Qsys Platform Designer and open qsys.qsys
    • (Optional) Under System Contents, double-click onchip_memory2_0 and under memory initialization provide your bootrom.mif file. Per default the bootrom.mif in the quartus folder will be used.
    • (Optional) Save and Generate the Qsys system.
  • Compile the project and program it onto the FPGA using either OpenOCD or USB-Blaster.

After programming:

Characters written are looped back and displayed.
  • If the red LED on the module starts blinking once per second, the FPGA was programmed successfully.
  • If the green LED on the module starts blinking once every two seconds, the RISC-V Core and its firmware is working.
  • PMod J2 will output a binary counter.
  • You can use the UART of the FPGA by using standard tools such as picocom:
    $ sudo picocom -b 115200 /dev/ttyACM0
    • Every character written is looped back and should be displayed on the terminal.