RISC-V & FreeRTOS - Revision history

Js at 16:19, 9 November 2021

2021-11-09T16:19:08Z

Js: Replaced content with "'''Under construction.''' For now follow the guide from the [https://github.com/ARIES-Embedded/riscv-on-max10/blob/master/GettingStarted.md repository]."

2021-11-05T12:37:15Z

Replaced content with "'''Under construction.''' For now follow the guide from the [https://github.com/ARIES-Embedded/riscv-on-max10/blob/master/GettingStarted.md repository]."

Dk: /* Compiling Firmware */

2021-05-27T12:59:49Z

‎Compiling Firmware

Dk: /* Downloads */

2021-05-27T12:58:39Z

‎Downloads

Js at 12:36, 5 November 2019

2019-11-05T12:36:55Z

Js at 11:27, 4 June 2019

2019-06-04T11:27:08Z

Js at 11:25, 4 June 2019

2019-06-04T11:25:48Z

Js at 11:25, 4 June 2019

2019-06-04T11:25:24Z

Js at 11:22, 4 June 2019

2019-06-04T11:22:45Z

Js at 08:07, 4 June 2019

2019-06-04T08:07:32Z

← Older revision		Revision as of 16:19, 9 November 2021
Line 1:		Line 1:
−	~~'''Under construction.'''~~	+	== Prerequisites ==

−	~~For now follow~~ the ~~guide~~ from the [https://github.com/ARIES-Embedded/riscv-on-max10/~~blob~~/~~master~~/~~GettingStarted~~.md repository].	+	* Linux Operating System (this guide uses Ubuntu 20.04)
		+	* Developer Tools (git, make, gcc, python (3))
		+	* [http://fpgasoftware.intel.com/?edition=lite Quartus Prime] (this guide uses version 20.1 Lite)
		+	* USB Blaster or [[Installing OpenOCD\|OpenOCD]]
		+	* SpiderSoM-S, MX10-S8 or MX10-U
		+	* optionally [https://shop.aries-embedded.de/tools/pmod/302/pmod-8ld?c=88 LED Pmod]
		+
		+	'''Note:'''<br>
		+	Instructions starting with '''$''' are commands to be executed in the terminal.<br>
		+	The working directory is to be taken from context.
		+
		+	== RISC-V Cores ==
		+
		+	Three open source RISC-V cores have been made available for the Intel Platform Designer (Qsys).
		+
		+	* [https://github.com/olofk/serv SERV]
		+	* [https://github.com/cliffordwolf/picorv32 PicoRV32]
		+	* [https://github.com/SpinalHDL/VexRiscv VexRiscv]
		+
		+	To install the cores for Intel Platform Designer, first download the source from the [https://github.com/ARIES-Embedded/riscv-on-max10 GitHub repository].
		+	:'''$''' <nowiki> git clone https://github.com/ARIES-Embedded/riscv-on-max10.git </nowiki>
		+	Then copy the cores to a location such as '''/opt/riscv-cores'''
		+	:'''$''' cp --parents riscv-on-max10/RiscvCores /opt/riscv-cores
		+	Start Intel Quartus Prime and add the cores to the global library:
		+	: Open the menu '''Assignments''' -> '''Settings'''
		+	: Under '''IP Settings''' -> '''IP Catalog Search Locations''' add the path
		+	: '''/opt/riscv-cores/*/''' to the global IP search directories
		+	Now the cores are available as IP under the group ''RISC-V''.
		+
		+	== Programming The Demo ==
		+
		+	=== Compiling Firmware ===
		+
		+	A precompiled memory initialization file (.mif) is available in the '''Prebuild/''' folder, that can be used to skip this section.
		+
		+	==== Installing The GNU GCC Toolchain ====
		+
		+	The complete guide for installing the toolchain can be found in the [https://github.com/riscv-collab/riscv-gnu-toolchain RISC-V GNU Toolchain repository].
		+
		+	Download and install the prerequisites:
		+	: '''$''' sudo apt-get install autoconf automake autotools-dev curl python3 libmpc-dev libmpfr-dev libgmp-dev gawk build-essential bison flex texinfo gperf libtool patchutils bc zlib1g-dev libexpat-dev
		+	Clone the repository:
		+	: '''$''' git clone https://github.com/riscv-collab/riscv-gnu-toolchain
		+	Configure build with multilib support for RV32 architectures:
		+	: '''$''' cd riscv-gnu-toolchain
		+	: '''$''' ./configure --prefix=/opt/riscv --with-multilib-generator="rv32i-ilp32--;rv32im-ilp32-rv32ima-;rv32imc-ilp32-rv32imac-;rv32imafc-ilp32f--"
		+	Finally start the build, note that this can take some time!
		+	: '''$''' sudo make
		+	Add the build tools to the path variable by opening '''~/.bashrc''' or equivalent and add the line:
		+	: export PATH="$PATH:/opt/riscv/bin"
		+	Reload the terminal:
		+	: '''$''' source ~/.bashrc
		+	Now the build tools are available via:
		+	: '''riscv64-unknown-elf-(*)
		+
		+	==== Compiling The RISC-V Firmware ====
		+
		+	Open a terminal in the '''RiscvSimple/''' or '''RiscvFreertos/''' folder of one of the sample projects and run the command:
		+	:'''$''' make
		+	If successful the output files are generated in the subfolder '''out/'''.<br>
		+	Copy the '''bootrom.mif''' to the respective Quartus Project folder.
		+	:'''$''' cp out/bootrom.mif ..
		+
		+	=== Quartus Prime Project ===
		+
		+	==== Precompiled Files ====
		+
		+	Precompiled programming files are available for the modules, they can be used to skip the next section and start with [[#Programming the FPGA\|programming the FPGA]].
		+
		+	==== Compiling The Quartus Project ====
		+
		+	Start Quartus Prime and open the project corresponding to your module.<br>
		+	Click on '''Start Compilation'''
		+	If successful, the programming files are generated in the folder '''output_files'''
		+
		+	==== Programming the FPGA ====
		+
		+	The FPGA stores its configuration in the internal SRAM.
		+	The configuration is lost when the device is powered down.
		+	At bootup the FPGA loads the configuration image from the internal FLASH to the SRAM.
		+	The '''.sof''' file will only write to the SRAM, usually used for testing and debugging,
		+	whereas the '''.pof''' file writes to the FLASH and reboots the FPGA. This image will then be loaded whenever the FPGA is powered on. The '''.pof''' file is usually used for deploying.
		+
		+	===== Programming Via USB-Blaster =====
		+
		+	Start Quartus Prime and open the Programmer.
		+	If no programming file is specified, click '''Add File''' and navigate to the '''Prebuild/''' or '''output_files''' folder and select the appropriate file for the module.
		+	Then under '''Hardware Setup...''' select the USB-Blaster.
		+	Finally press Start.
		+
		+	===== Programming Via OpenOCD =====
		+	If not done already install and configure [[Installing OpenOCD\|OpenOCD]].
		+	Then open a terminal and use the command with the '''.svf''' file:
		+	: '''$''' mx10spider_prog ''<path/to/file.svf>''
		+	Example: To program the SpiderSoM with the prebuild "'''.sof'''" file.
		+	: '''$''' mx10spider_prog Prebuild/Spider_S.svf

← Older revision		Revision as of 12:37, 5 November 2021
Line 1:		Line 1:
−	~~== Prerequisites ==~~	+	'''Under construction.'''

−	* Linux Operating System (this guide ~~uses Ubuntu 16.04)~~	+	For now follow the guide from the [https://github.com/ARIES-Embedded/riscv-on-max10/blob/master/GettingStarted.md repository].
−	* Utility Software (git, make, python)
−	* [http://fpgasoftware.intel.com/?edition=lite Quartus Prime]
−	* A [[Spiderboard_SoM\|SpiderSoM]] or MX10<sup>[[Installing OpenOCD#MX10 Hardware Issue\|[note]]]</sup> with atleast 8K LE, [[Spiderboard_Baseboard\|SpiderBase]], optionally [https://shop.aries-embedded.de/tools/pmod/302/pmod-8ld?c=88 LED Pmod]
−	* One of the following:
−	** [[Installing OpenOCD\|OpenOCD]]
−	** USB Blaster and Quartus Programmer
−
−	~~== Installing VectorBlox ORCA Core and RISC-V Tools ==~~
−
−	* Download the ~~source from~~ [https://github.com/~~VectorBlox/orca https://github.com/VectorBlox/orca] using git.~~
−	*: This guide uses the install locations ''/opt/orca/'' and ''/opt/riscv/'', you can substitute them if you wish.
−	* Open a terminal window and run:
−	*: '''$''' <nowiki> git clone https://github.com/VectorBlox/orca.git /opt/orca </nowiki>
−	*: '''$''' cd /opt/orca/tools/riscv-toolchain/
−	*: '''$''' export RISCV_INSTALL="/opt/riscv"
−	*: '''$''' ./build-toolchain.sh
−	*:: Info: This may take a while.
−	* Finally, add the RISC-V tools to your path. Open ''.profile'' in your home directory with a text exitor and add the line:
−	*: PATH="/opt/riscv/bin:$PATH"
−	* After updating the path variable you may need to logout and login again or run the following command in the terminal:
−	*: '''$''' source ~/.profile
−
−	~~== Compiling Firmware ==~~
−
−
−
−	* Download the [https://downloads.aries-embedded.de/products/MX10/software/demo/20190604_mx10_spider_riscv_freertos.zip RISC-V & FreeRTOS Example] and unpack.
−	* Then choose either RISC-V or RISC-V & FreeRTOS and run make.
−	* Open a terminal window and run the commands:
−	*: '''$''' wget <nowiki>https://downloads.aries-embedded.de/products/MX10/software/demo/20190604_mx10_spider_riscv_freertos.zip</nowiki>
−	*: '''$''' unzip 20190604_mx10_spider_riscv_freertos.zip
−	** For the RISC-V standalone demo:
−	**: '''$''' cd mx10_spider_riscv_freertos/riscv
−	** Or for RISC-V with FreeRTOS:
−	**: '''$''' cd mx10_spider_riscv_freertos/riscv_freertos
−	*: '''$''' make
−	* This will create the ''bootrom.mif'' (Memory Initialization File) in the subfolder ''out''.
−	* Copy the ''bootrom.mif'' to ''mx10_spider_riscv_freertos/quartus_mx10'' or ''mx10_spider_riscv_freertos/quartus_spider'', depending on which module you use.
−	*: '''$''' cp out/bootrom.mif ../quartus_spider
−
−	~~[[File:terminal_make_riscv.png\|1200px\|Terminal after calling make.]]~~
−
−	~~== Quartus Prime Project ==~~
−
−	* Open Quartus Prime and load the project under ''mx10_spider_riscv_freertos/quartus_mx10'' or ''mx10_spider_riscv_freertos/quartus_spider''
−	* Open Device Settings (Assigments -> Device) and select your FPGA, the default FPGA the MX10 project is the 10M08DAF256C8G FPGA and for the SpiderSoM project the 10M08SAU169C8G FPGA.
−	* Open '''Assignments -> Settings -> IP Settings -> IP Catalog Search Locations''' and add the search path to ORCA.
−	: If ORCA was installed under ''/opt/orca/'' then type in as search path ''/opt/orca//'' and click on the ''Add'' button.
−	~~[[File:quartus_setting_iploc.png\|700px\|Type in the search path and then click on ''Add''.]]~~
−	* (Optional) Launch Qsys Platform Designer and open ''qsys.qsys''
−	** (Optional) Under System Contents, double-click ''onchip_memory2_0'' and under memory initialization provide your bootrom.mif file. Per default the bootrom.mif in the quartus folder will be used.
−	** (Optional) Save and Generate the Qsys system.
−	~~[[File:qsys-ram-init.png\|900px\|Setting the memory initialization in Qsys Platform Designer]]~~
−	* Compile the project and program it onto the FPGA using either [[Getting Started: Quartus Prime & OpenOCD#Programming via OpenOCD \| OpenOCD]] or [[Getting Started: Quartus Prime & OpenOCD#Programming via USB Blaster\| USB-Blaster]].
−
−
−	~~After programming:~~
−
−	* If the red or orange LED on the module starts blinking once per second, the FPGA was programmed successfully.
−	* If the green LED on the module starts blinking once every two seconds, the RISC-V Core and its firmware is working.
−	* PMod J2 will output a binary counter.
−	* You can use the UART of the FPGA by using standard tools such as picocom:
−	*: '''$''' sudo picocom -~~b 115200 /dev~~/~~ttyACM0~~
−	** Every character written is looped back and should be displayed on the terminal.
−
−
−	~~<div><ul>~~
−	~~<li style="display: inline-block;"> [[File:spider-running-~~riscv-~~leds.png\|x330px\|thumb\|Spider with LED PMod connected~~ on ~~J2 showing the binary counter. The LED PMod can be acquired in the [https://shop.aries-embedded.de/tools/pmod/302/pmod-8ld?c=88 shop]]] </li>~~
−	~~<li style="display: inline~~-~~block;"> [[File:terminal_picocom.png\|x330px\|thumb\|Characters written are looped back and displayed.]] </li>~~
−	~~</ul><~~/~~div>~~
−
−
−	~~== Downloads ==~~
−
−	* [https://~~github~~.~~com/VectorBlox/orca VectorBlox ORCA~~]
−	* [https://downloads.aries-embedded.~~de/products/MX10/software/demo/20190604_mx10_spider_riscv_freertos.zip RISC-V & FreeRTOS Example]~~

@@ Line 28: / Line 28: @@
-* Download the [ftp://ftp.aries-embedded.de/products/MX10/software/demo/20190604_mx10_spider_riscv_freertos.zip RISC-V & FreeRTOS Example] and unpack.
+* Download the [https://downloads.aries-embedded.de/products/MX10/software/demo/20190604_mx10_spider_riscv_freertos.zip RISC-V & FreeRTOS Example] and unpack.
 * Then choose either RISC-V or RISC-V & FreeRTOS and run make.
 * Open a terminal window and run the commands:
-*: '''$''' wget <nowiki>ftp://ftp.aries-embedded.de/products/MX10/software/demo/20190604_mx10_spider_riscv_freertos.zip</nowiki>
+*: '''$''' wget <nowiki>https://downloads.aries-embedded.de/products/MX10/software/demo/20190604_mx10_spider_riscv_freertos.zip</nowiki>
 *: '''$''' unzip 20190604_mx10_spider_riscv_freertos.zip
 ** For the RISC-V standalone demo:

← Older revision		Revision as of 12:58, 27 May 2021
Line 77:		Line 77:

	* [https://github.com/VectorBlox/orca VectorBlox ORCA]		* [https://github.com/VectorBlox/orca VectorBlox ORCA]
−	* [~~ftp~~://~~ftp~~.aries-embedded.de/products/MX10/software/demo/20190604_mx10_spider_riscv_freertos.zip RISC-V & FreeRTOS Example]	+	* [https://downloads.aries-embedded.de/products/MX10/software/demo/20190604_mx10_spider_riscv_freertos.zip RISC-V & FreeRTOS Example]

@@ Line 4: / Line 4: @@
 * Utility Software (git, make, python)
 * [http://fpgasoftware.intel.com/?edition=lite Quartus Prime]
-* A [[Spiderboard_SoM|SpiderSoM]] or MX10<sup>[[Installing OpenOCD#MX10 Hardware Issue|[note]]]</sup> with atleast 8K LE, [[Spiderboard_Baseboard|SpiderBase]]
+* A [[Spiderboard_SoM|SpiderSoM]] or MX10<sup>[[Installing OpenOCD#MX10 Hardware Issue|[note]]]</sup> with atleast 8K LE, [[Spiderboard_Baseboard|SpiderBase]], optionally [https://shop.aries-embedded.de/tools/pmod/302/pmod-8ld?c=88 LED Pmod]
 * One of the following:
 ** [[Installing OpenOCD|OpenOCD]]
@@ Line 69: / Line 69: @@
 <div><ul>
-<li style="display: inline-block;"> [[File:spider-running-riscv-leds.png|x330px|thumb|Spider with LED PMod connected on J2 showing the binary counter.]] </li>
+<li style="display: inline-block;"> [[File:spider-running-riscv-leds.png|x330px|thumb|Spider with LED PMod connected on J2 showing the binary counter. The LED PMod can be acquired in the [https://shop.aries-embedded.de/tools/pmod/302/pmod-8ld?c=88 shop]]] </li>
 <li style="display: inline-block;"> [[File:terminal_picocom.png|x330px|thumb|Characters written are looped back and displayed.]] </li>
 </ul></div>

@@ Line 47: / Line 47: @@
 * Open Quartus Prime and load the project under ''mx10_spider_riscv_freertos/quartus_mx10'' or ''mx10_spider_riscv_freertos/quartus_spider''
-* Open Device Settings (Assigments -> Device) and select your FPGA, the default FPGAs are:
+* Open Device Settings (Assigments -> Device) and select your FPGA, the default FPGA the MX10 project is the 10M08DAF256C8G FPGA and for the SpiderSoM project the 10M08SAU169C8G FPGA.
 * Open '''Assignments -> Settings -> IP Settings -> IP Catalog Search Locations''' and add the search path to ORCA.
 *: If ORCA was installed under ''/opt/orca/'' then type in as search path ''/opt/orca/**/*'' and click on the ''Add'' button.

@@ Line 48: / Line 48: @@
 * Open Quartus Prime and load the project under ''mx10_spider_riscv_freertos/quartus_mx10'' or ''mx10_spider_riscv_freertos/quartus_spider''
 * Open Device Settings (Assigments -> Device) and select your FPGA, the default FPGAs are:
-** MX10 SoM project: 10M08DAF256C8G FPGA
+** MX10 SoM project: '''10M08DAF256C8G''' FPGA
-** SpiderSoM project: 10M08SAU169C8G FPGA
+** SpiderSoM project: '''10M08SAU169C8G''' FPGA
 * Open '''Assignments -> Settings -> IP Settings -> IP Catalog Search Locations''' and add the search path to ORCA.
 *: If ORCA was installed under ''/opt/orca/'' then type in as search path ''/opt/orca/**/*'' and click on the ''Add'' button.

@@ Line 28: / Line 28: @@
-* Download the [ftp://ftp.aries-embedded.de/products/MX10/software/demo/20190506_SpiderSoM_quartus_riscv_freertos.zip RISC-V & FreeRTOS Example] and unpack.
+* Download the [ftp://ftp.aries-embedded.de/products/MX10/software/demo/20190604_mx10_spider_riscv_freertos.zip RISC-V & FreeRTOS Example] and unpack.
 * Then choose either RISC-V or RISC-V & FreeRTOS and run make.
 * Open a terminal window and run the commands:
-*: '''$''' wget <nowiki>ftp://ftp.aries-embedded.de/products/MX10/software/demo/20190506_SpiderSoM_quartus_riscv_freertos.zip</nowiki>
+*: '''$''' wget <nowiki>ftp://ftp.aries-embedded.de/products/MX10/software/demo/20190604_mx10_spider_riscv_freertos.zip</nowiki>
-*: '''$''' unzip 20190506_SpiderSoM_quartus_riscv_freertos.zip
+*: '''$''' unzip 20190604_mx10_spider_riscv_freertos.zip
 ** For the RISC-V standalone demo:
-**: '''$''' cd riscv_freertos_example/riscv
+**: '''$''' cd mx10_spider_riscv_freertos/riscv
 ** Or for RISC-V with FreeRTOS:
-**: '''$''' cd riscv_freertos_example/riscv_freertos
+**: '''$''' cd mx10_spider_riscv_freertos/riscv_freertos
 *: '''$''' make
 * This will create the ''bootrom.mif'' (Memory Initialization File) in the subfolder ''out''.
-* Copy the ''bootrom.mif'' to ''riscv_freertos_example/quartus''
+* Copy the ''bootrom.mif'' to ''mx10_spider_riscv_freertos/quartus_mx10'' or ''mx10_spider_riscv_freertos/quartus_spider'', depending on which module you use.
-*: '''$''' cp out/bootrom.mif ../quartus
+*: '''$''' cp out/bootrom.mif ../quartus_spider
 [[File:terminal_make_riscv.png|1200px|Terminal after calling make.]]
@@ Line 46: / Line 46: @@
 == Quartus Prime Project ==
-* Open Quartus Prime and load the project under ''riscv_freertos_example/quartus''.
+* Open Quartus Prime and load the project under ''mx10_spider_riscv_freertos/quartus_mx10'' or ''mx10_spider_riscv_freertos/quartus_spider''
-* Open Device Settings (Assigments -> Device) and select your FPGA.
+* Open Device Settings (Assigments -> Device) and select your FPGA, the default FPGAs are
-*: INFO: This Quartus project is specific to the SpiderSoM - for the MX10 the pin assignment has to be changed.
+** MX10 SoM project: 10M08DAF256C8G FPGA
 * Open '''Assignments -> Settings -> IP Settings -> IP Catalog Search Locations''' and add the search path to ORCA.
 *: If ORCA was installed under ''/opt/orca/'' then type in as search path ''/opt/orca/**/*'' and click on the ''Add'' button.
@@ Line 61: / Line 62: @@
 After programming:
-* If the red LED on the module starts blinking once per second, the FPGA was programmed successfully.
+* If the red or orange LED on the module starts blinking once per second, the FPGA was programmed successfully.
 * If the green LED on the module starts blinking once every two seconds, the RISC-V Core and its firmware is working.
 * PMod J2 will output a binary counter.
@@ Line 78: / Line 79: @@
 * [https://github.com/VectorBlox/orca VectorBlox ORCA]
-* [ftp://ftp.aries-embedded.de/products/MX10/software/demo/20190506_SpiderSoM_quartus_riscv_freertos.zip RISC-V & FreeRTOS Example]
+* [ftp://ftp.aries-embedded.de/products/MX10/software/demo/20190604_mx10_spider_riscv_freertos.zip RISC-V & FreeRTOS Example]